This application is based upon and claims priority from prior French Patent Application No. 0107717, filed Jun. 13, 2001, the disclosure of which is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention generally relates to integrated circuits and their fabrication. More particularly, the invention relates to fabricating bipolar transistors, diodes, and other types of active components.
2. Description of Related Art
In prior art of vertical bipolar transistors, the collector, the base, and the emitter are formed by superposing layers vertically, i.e. in the direction normal to the surface of the substrate.
Doping some layers by ion implantation, which is known in the art, takes place after forming the layers. Ion implantation is effected by bombarding the top surface of an integrated circuit wafer with dopant ions in the direction of the layers to be doped, the ions traveling through a certain thickness of material and then stops. Although ion implantation is useful, it is not without its shortcomings. One shortcoming is that ion implantation modifies the crystal structure of the monocrystalline silicon used in the layers or the substrate, and even destroys it locally by creating defects that compromise the operation of the integrated circuit. Accordingly, a need exists to overcome this shortcoming.
The present invention is a simple method of fabricating a self-aligned integrated circuit active component with high quality monocrystalline silicon areas.
The fabrication method in accordance with one embodiment of the present invention is for fabricating an integrated circuit including a monocrystalline silicon substrate having a top surface, at least one layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion. Annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone, the first dopant dominating in the first zone. Stated differently, the first dopant exists in a higher concentration in the first zone than the concentration of the other dopants.
In the case of a bipolar transistor, the emitter and the intrinsic base are therefore formed by an annealing step that is economical and easy to control.
In one embodiment of the invention a buried layer can first be formed in the substrate.
In one embodiment of the invention a bipolar transistor is fabricated, for example using the BICMOS technology. The first zone forms the intrinsic emitter and the second zone forms the intrinsic base. The extrinsic base is formed during annealing in a third zone adjacent the second zone.
In one embodiment of the invention a well is formed to provide access to the buried layer from the top surface of the substrate.
In another embodiment, the first dopant is arsenic and the second dopant is boron.
In the case of a PNP bipolar transistor, the first dopant can be antimony and the second dopant can be phosphorus.
In another embodiment of the invention a diode disposed in a well formed in the substrate is fabricated.
To be more specific, an insulative layer is deposited on the top surface of the substrate, after which a first opening is excavated in the insulative layer. A layer of polysilicon is then deposited over the whole of the surface, after which the polysilicon layer is excavated to form a smaller second opening inside the first opening so that the edges of the second opening are of polysilicon and in contact with the top surface of the substrate. A top insulative layer is then deposited over the whole of the surface, after which a smaller third opening is excavated inside the second opening to expose the bottom of the third opening, with insulative material edges. This forms an emitter window.
Then a thick layer of polysilicon is deposited, consisting of a plurality of sublayers depending on the gas mixtures that are used to deposit the polysilicon. The thick layer of polysilicon includes a thin first sublayer, for example of the order of 100 angstrom units thick, doped with a first dopant and in contact with the top surface of the substrate in the bottom of the emitter window, and then a second sublayer doped with a second dopant, and then a third sublayer doped with the first dopant. The polysilicon layer is then etched away except inside the emitter window and an adjoining region.
The sublayers are doped in real time, at the same time as depositing the layer of polysilicon, by controlling the gas mixtures present in the reactor in which the integrated circuit is formed. For example, for doping with arsenic, arsine is introduced.
The subsequent annealing step causes fast downward diffusion of the second dopant, including through the first sublayer, and slower diffusion of the first dopant, which becomes dominant in the whole of the polysilicon layer, including in the second sublayer, and in the first zone of the substrate, adjoining the bottom of the emitter window. The faster diffusing second dopant is dominant in the second zone which is outside the first zone but nevertheless close to the bottom of the emitter window. The second zone is in contact with the third zone, which forms the extrinsic base.
As an alternative to the above, a supplementary sublayer of undoped polysilicon is provided in the thick doped silicon layer, the supplementary layer being disposed between the first and second sublayers and forming a kind of screen for slightly delaying the diffusion of the second dopant into the substrate by increasing the distance between the second sublayer and the substrate.
In further variants, the sublayers of the thick layer of polysilicon is doped by implanting the sublayers at different energies to vary the implantation depth, implantation in polysilicon being free of the dislocation drawbacks encountered in monocrystalline silicon.
For example, a layer of polysilicon from 1000 to 3000 xc3x85 thick, for example of the order of 2000 xc3x85 thick, is provided, and sublayers from 30 to 200 xc3x85 thick, for example of the order of 100 xc3x85 thick. The dopant concentration can be of the order of 1020.
One advantage of the invention is that cleaning the bottom of the emitter window, which is generally carried out after excavating the emitter window, does not cause any wear and consequently does not reduce the thickness of the base, which is yet to be formed at this location, but causes very slight wear of the substrate, which has no harmful effect. This achieves improved control and improved reproducibility of the thickness of the base. Also, the slow and costly step of implanting the base in the substrate is eliminated.
The dimensions of the first and second zones are easily controlled by adjusting the annealing temperature and time; the temperature is of the order of 600 to 900xc2x0 and the annealing time is of the order of a few minutes.
The invention has the further advantage that the intrinsic emitter and the intrinsic base are self-aligned in the sense that they are both formed by diffusing dopant from the emitter window. Finally, the method is extremely simple to put into practice using existing integrated circuit fabrication machines.
The integrated circuit in accordance with one aspect of the invention includes a monocrystalline silicon substrate having a top surface and at least one layer of polycrystalline silicon on the top surface of the substrate. The substrate has a first zone which is formed immediately under the polycrystalline silicon layer and in which a first dopant is dominant and a second zone around the first zone in which a second dopant having a different conductivity than the first dopant is dominant, the first and second dopants being also present in at least a portion of the polycrystalline silicon layer.
In one embodiment of the invention the substrate includes a third zone, flush with the top surface of the substrate, in contact with the second zone and doped with a third dopant whose conductivity is the same as that of the second dopant. The second and third dopants are advantageously identical. The third zone is advantageously more strongly doped than the second zone.
In one embodiment of the invention the first zone forms the intrinsic emitter of a bipolar transistor, the second zone forms the intrinsic base, and the third zone forms the extrinsic base of the same bipolar transistor.